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| EDFA and CW Laser Controller Preliminary Technical Data FEATURES Four Operational Modes Including: Constant Laser Current Constant Optical Output Power Constant EDFA Gain Constant Laser Power High Power Efficiency: >90% Three Built-In Photodiode TIAs Adjustable Laser Diode and EDFA Protection Limits Free-run or Synchronous Switching Frequency Modes Adjustable Phase Delay for Synchornous Clock Mode Optional Dithering Built-In Programmable Dither Frequency and Amplitude ADN8820* Output Power (COP), or Constant EDFA Gain (CG). Multiple pump laser applications are easily supported by the ADN8820. Common-cathode-to-ground and common-anode-to-VDD configurations are also supported. The ADN8820 has a high speed closed-loop control, making it suitable for add/drop applications in telecommunication systems. It has a low-current shutdown mode and a soft-start feature to minimize power supply bounce on start-up. Protection circuitry is built into the device. The protection limits are easily adjustable and are used to set maximum output current and voltage, optical output power, EDFA gain, and pump or CW laser power. The output stage consists of a high-efficiency PWM amplifier in parallel with a high-speed linear amplifier. This provides the fastest settling time response along with the lowest power and heat dissipation. A pair of external MOSFETs on the PWM amplifier provide output currents of up to 5A. Three low-bias current TIAs are built-in. These allow amplification for the laser back-facet photodiode and EDFA input and output photodiodes. For CW laser applications, the two unused TIAs can be used for etalon photodiode amplification, allowing continuous wavelength monitoring. The ADN8820 is available in a 7 x 7 mm lead-frame chip scale package (LFCSP) with a package height of less than 1 mm. APPLICATIONS EDFA Pump Laser Diode Control CW Laser Bias Control Raman Amplifiers GENERAL DESCRIPTION The ADN8820 is a versatile Continuous Wave (CW) and EDFA laser diode driver and controller. It provides a low noise and precise current control for driving a source or pump laser diode. It can be set to operate in one of four controller modes: Constant Current (CC), Constant Laser Power (CLP), Constant FUNCTIONAL BLOCK DIAGRAM * U.S. Patent Pending Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. ADN8820 - SPECIFICATIONS1 Parameter TRANSIMPEDANCE AMPLIFIERS Detection Range Symbol IIP IOP ILP IBIPDIN IBOPDIN IBLPDIN VBLP, VB VIPO VLPO VOPO VOSIP VOSOP VOSLP IOUTIPO IOUTLPO IOUTOPO GBWIP GBWOP GBWLP VINLIM VOSLIM VLIMNC IBLIM VIPMINLO IVLIM Conditions From IPDIN Photodiode From OPDIN Photodiode From LPDIN Photodiode IPDIN, OPDIN, LPDIN Amplifier Inputs Preliminary Technical Data Min 0.005 0.005 5 100 100 100 0 0 0 0 10 10 2 10 10 10 10 10 1 0 2.6 10 2.7 VDD VDD VDD VDD Typ Max 5,000 5,000 5,000 Unit A A A pA pA pA V V V V V V mV mA mA mA MHz MHz MHz V mV V nA mV A mV V V V mA MHz V A V Table 1. ADN8820--Electrical Characteristics (AVDD = PVDD = 5V, AGND = PGND = 0V, TA = 25C, using typical circuit in Figure 1, unless otherwise noted.)2 Input Bias Current Input Voltage Range Monitor Output Range IPO, LPO, OPO Outputs Input Offset Voltage IPDIN, OPDIN, LPDIN Amplifiers Maximum Output Current IPO, LPO, OPO Outputs Gain-Bandwidth Product IPDIN, OPDIN, LPDIN Amplifiers LIMIT CONTROLS Input Voltage Range Limiter Accuracy Open Circuit Voltage Pull-up Current IPMIN Disable Threshold VLIM Input Bias Current VLIM Voltage Control Accuracy ERROR AMPLIFIER Input Offset Voltage Input Common-Mode Voltage Range Output Voltage Swing Maximum Output Current Gain-Bandwidth SET INPUT Input Voltage Range Input Bias Current MULTIPLEXERS Ouput Impedance Output Voltage Range IPMIN, OPLIM, LPLIM, ILIM, and VLIM OPLIM, LPLIM, ILIM, IPMIN Voltage for OPLIM, LPLIM, and ILIM with no connection Flowing out of OPLIM, LPLIM, and ILIM with LIM Voltage <2.0V VIPO = 0V Flowing into VLIM pin |VLINOUT - VLIM| 2.5 2.6 500 200 1 50 10 0 0 10 10 0 1 100 0 VDD VDD 25 VDD VDD VOSEA VCMEA VOUTEA IMAXEA GBWEA VSET IBSET 1 2 Specifications subject to change without notice Capital letters denote pin names. Rev. PrB | Page 2 of 9 ADN8820 - SPECIFICATIONS1 Parameter LINEAR OUTPUT Short-Circuit Output Current Output Voltage Compliance Power Supply Rejection Ratio Gain-Bandwidth Product PWM OUTPUT Offset Voltage Non-Overlap Delay Output Transistion Time Output Driver Resistance Output Current Ripple Soft-Start Time Standby Mode Threshold OSCILLATOR Free-Run Oscillation Frequency Synchornization Capture Range Phase Adjustment CURRENT SENSE AMPLIFIER Input Common-Mode Voltage Range Input Resistance Output Offset Voltage Gain Output Voltage Range DITHER GENERATOR Frequency Range Frequency Multiplier Programming Voltage Dither Current Control Votlage Programming Current Range Maximum DO Output Current DO Output Voltage POWER SUPPLY Power Supply Range Supply Current Shutdown Current Standby Current Undervoltage Lockout REFERNCE OUTPUT Reference Voltage Power Supply Rejection Ratio Symbol IOUTLIN VLINMAX VLINMIN PSRRLIN GBWLIN VOSPWM tR, tF RNGATE RPGATE Conditions Preliminary Technical Data Min 300 4.5 0.5 68 10 VOSPWM = LINOUT - FB FET CISS 3nF 40 6 6 1 15 0.4 100 100 45 0 VCSP = VCSN = 2.5V VLIO / (VCSP - VCSN) 0 xx k RT xx k See Table II VLIO = 2.5 V VLIO = 2.5 V 0.2 10.5 1 20 VDD 2 1,000 1,000 315 VDD 10 Typ Max Unit mA V V dB MHz mV ns % ms V kHz kHz degrees V k mV V/V V MHz Table 1. ADN8820--Electrical Characteristics (AVDD = PVDD = 5V, AGND = PGND = 0V, TA = 25C, using typical circuit in Figure 1, unless otherwise noted.)2 IOUTLIN = 300mA (sourcing) IOUTLIN = -160mA (sinking) VSSSB fCLK CLK VCMCS RINCS VOSLIO AVCS VLIO fDITHER IOUT = 300mA, VOUT = 2V CSS = 0.1 F PWM and LINOUT disabled CMPOSC = VDD; SYNCIN = 0V SYNCIN driven with external clock VDCTL IDCTL IMAXDO VDO VDD ISY ISD ISB VUVLO VREF PSRRREF 1.2 0 19 1.25 20 1.5 1.3 100 21 V A mA V V mA A mA V V V 3.0 DSEL/SD 0.8V; IOUT = 0A -40C TA +85C DSEL/SD 0.2V SS/SB 0.2V 25 10 2.5 2.4 2.4 2.5 68 5.5 30 2.5 2.6 IREF 2 mA With respct to AVDD 1 2 Specifications subject to change without notice Capital letters denote pin names. Rev. PrB | Page 3 of 9 ADN8820 - SPECIFICATIONS1 Parameter DUAL OUTPUT Output Voltage Range Voltage Gain CONTROL LOOP STATUS OUTPUT CLGD High CLGD Low LOGIC CONTROL Logic Low Input Threshold Logic High Input Threshold Logic Low Output Level Logic High Output Level Input Current Symbol VDUAL AVDUAL Conditions IDUAL 500 A AVDUAL = DUAL / LIO; VILIM = 2.25V with 1.9 V VLIO 2.1V 0.05 x VDD VEAOUT 0.95 x VDD Otherwise MODE0, MODE1, SYNCIN MODE0, MODE1, SYNCIN Preliminary Technical Data Min 0.4 20 Typ Max VDD-0.4 Unit V V/V Table 1. ADN8820--Electrical Characteristics (AVDD = PVDD = 5V, AGND = PGND = 0V, TA = 25C, using typical circuit in Figure 1, unless otherwise noted.)2 VCLGDHI VCLGDLO VIL VIH VOL VOH 4.8 0.2 0.2 VDD-0.2 0.2 VDD-0.2 1 V V V V V V A 1 2 Specifications subject to change without notice Capital letters denote pin names. Figure 1. Typical Application Circuit Rev. PrB | Page 4 of 9 ADN8820 ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings (at 25C, unless otherwise noted) Parameter Supply Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range: CP Packages Lead Temperature Range (Soldering, 60 Sec) Rating 6V Indefinite -65C to +150C -40C to +85C -65C to +150C 300C Preliminary Technical Data Table 3. Thermal Resistance Package Type LFSCP-48 (CP-48) JA1 32 JC 12 Unit C/W 1 JA is specified for the worst-case conditions, i.e., JA is specified for device soldered in circuit board for surface mount packages. Figure 2. System Block Diagram PIN CONFIGURATION Rev. PrB | Page 5 of 9 ADN8820 PIN FUNCTIONS Name Pin AMPLIFIER INPUTS IPDIN 3 LPDIN 6 OPDIN 9 VB 2 VBLP 5 CSP 37 CSN 38 Function Input to TIA for EDFA input photodiode Input to TIA for laser photodiode Input to TIA for EDFA output photodiode Bias voltage for EDFA input and output photodiodes Bias voltage for laser photodiode Non-inverting input of current sense amplifier Inverting input of current sense amplifier Preliminary Technical Data Connections EDFA input photodiode and feedback resistor Laser photodiode and feedback resistor EDFA output photodiode and feedback resistor External bias voltage required External bias voltage required High-side of laser current sense resistor (50 m typ.) Low-side of laser current sense resistor (50 m typ.) External voltage required External voltage or no connection (defaults to 2.5 V) External voltage or no connection (defaults to 2.5 V) External voltage or no connection (defaults to 2.5 V) External voltage required Internally connects inverting input of EA to laser diode compensation network Internally connects inverting input of EA to EDFA compensation network Internal connection to linear output amplifier Connects to two external compensation networks: one for EDFA loop, one for laser diode loop R-C network to ground External voltage or DAC LIMIT INPUTS VLIM 1 Laser diode voltage will not exceed VLIM ILIM 45 Limits output voltage if LIO > ILIM OPLIM 47 Limits output voltage if OPO > OPLIM LPLIM 46 Limits output voltage if LPO > LPLIM IPMIN 48 Limits output voltage if IPO is lower than IPMIN ERROR (COMPENSATION) AMPLIFIER (EA) EANLP 41 Compensation network for laser diode loop EANOP EAOUT MUX 40 39 42 Compensation network for EDFA loop Output of compensation amplifier Allows separate compensation for EDFA and laser diode OPCMP 44 Compensation for limiter section SET 8 Sets output power or current based on MODE settings POWER OUTPUT AMPLIFIERS LINOUT 33 Linear amplifier output PGATE 30 PWM switching for PMOS NGATE 31 PWM switching for NMOS SWITCH 28 PWM amplifier output FB 24 Feedback input for PWM amplifier PWMCMP1 23 Compensation for PWM amplifier PWMCMP2 22 Compensation for PWM amplifier 25 Constant current charges external capacitor to softSS/SB start PWM output from 0% duty cycle OUTPUT MONITOR VOLTAGES IPO 4 Output of EDFA input photodiode TIA OPO 10 Output of EDFA output photodiode TIA LPO 7 Output of laser diode photodiode TIA LIO 11 Output of current sense amplifier DUAL 12 Compares LIO to 90% of ILIM EAOUT 39 OSCILLATOR SECTION SYNCIN 27 SYNCOUT 26 CMPOSC PHASE RT 16 17 15 Output of compesnation amplifier Optional clock input signal for PLL Follows rising edge of SYNCIN plus phase shift Compensation for synchronizing PLL Sets rising edge phase shift of SYNCOUT Sets PWM clock frequency Laser diode through 1 series resistor Gate of external PMOS for PWM output Gate of external NMOS for PWM output Drains of external NMOS, PMOS, and input of L-C filter Output of L-C filter and laser diode Series R-C networks to FB and PWMCMP2 Series R-C to PWMCMP1 Optional external FET can pull down and to engage standby mode Feedback resistor to IPDIN Feedback resistor to OPDIN Feedback resistor to LPDIN To SET pin of additional ADN8820 device in multipump optical amplifier applications Internal connection to linear output amplifier Ground or external clock Optional connection to SYNCIN of additional ADN8820 device R-C network to ground External voltage or no connection (default is 0.7V) Resistor (RT) to ground Rev. PrB | Page 6 of 9 ADN8820 Name Pin DITHER GENERATOR 21 DSEL/SD DCTL DO LOGIC INPUTS MODE1 MODE0 DSEL/SD SS/SB 36 35 18 19 21 25 Function 4-level logic input to set dither frequency or engage shutdown Sets dither current as a percentage of the laser diode current Optional dither AC current to laser diode Sets control loop mode (see Table I) Sets control loop mode (see Table I) Pulling voltage low engages shutdown Pulling voltage low engages standby Preliminary Technical Data Connections External voltage Resistor (RDCTL) to ground To laser diode through 1 nF series capacitor External logic voltage External logic voltage External voltage 470 pF soft-start capacitor to ground; optional external FET can pull down to engage standby LOGIC OUTPUTS CLGD 20 POWER PVDD AVDD PGND AGND VREF Logic high if EAOUT is within 5% to 95% of AVDD; Logic low otherwise Power for output amplifiers and digital sections Low noise power for TIAs, limiter section, and EA Current return for output amplifiers Low noise ground 2.5 V reference voltage 3.0 V to 5.5 V 3.0 V to 5.5 V 0V 0V Can be used as refernce for VB, VBLP, SET, and limiter inputs 29, 34 43 32 14 13 TABLE 4. MODE CONTROL LOGIC MODE Inputs MODE1 MODE0 0 0 0 1 1 1 0 1 Mode Setting Constant Current Constant Laser Power Constant Ouptut Power Constant Gain Error Amplifier -Input +Input EANLP SET EANLP EANOP EANOP SET SET IPO MUX Output LIO LPO OPO OPO Description Maintains a fixed current through laser diode; generally used for calibration. Maintains a constant optical output power from laser diode. Maintains a constant optical power at output of EDFA. Monitors both input and output optical power to maintain constant gain from optical amplifier. TABLE 5. PWM CLOCK FREQUENCY SELECTION LEVELS DSEL/SD Min 0 0.7 1.3 2.0 (V) Max 0.5 1.2 1.8 VDD PWM Clock Frequency Mode Shutdown Active Active Active Division N/A fDITHER /2 fDITHER /4 fDITHER /8 Note: fDITHER is the ADN8820 dither frequency and is set by a resistor connected from RT to ground. Rev. PrB | Page 7 of 9 ADN8820 OUTLINE DIMENSIONS Preliminary Technical Data Figure 3. 48-Lead Frame (LFCSP-48) Chip Scale Package 7 x 7 mm Body (CP-48) Dimensions Shown in Millimeters ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these products feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrB | Page 8 of 9 ADN8820 ORDERING GUIDE Table 6. ADN8820 Ordering Guide Product ADN8820 ADN8820-REEL7 ADN8820-EVAL Package Description 48-Lead LFCSP 48-Lead LFCSP Eval board Package Option CP-48 CP-48 N/A Top Mark TBD TBD N/A No. of Parts per Reel N/A TBD N/A Preliminary Technical Data Temperature Range (C) -40 to +125 -40 to +125 -40 to +125 (c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C02747-0-4/03(C) Rev. PrB | Page 9 of 9 |
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